This invention relates to electrical test equipment for semiconductor devices. More specifically, the invention relates to an improved apparatus and method for electrically connecting semiconductor die to temporary test carriers used to perform static dynamic burn-in and full electrical testing.
Semiconductor die are subjected to a series of test procedures in order to assure quality and reliability. This testing procedure conventionally includes xe2x80x9cprobe testingxe2x80x9d in which individual dice, while still on a wafer, are initially tested to determine functionality and speed. Probe cards are used to electrically test die at that level, and probe cards interface with single or multiple die at a time in wafer. If the wafer has a yield of functional dice that indicates the quality of the functional dice is likely to be good, each individual die is assembled in a package to form a semiconductor device. Conventionally, the packaging includes a lead frame and a plastic or ceramic housing.
These completed semiconductor devices are mated to a test carrier to connect the semiconductor device to various test circuits. The packaged devices are then subjected to another series of tests that include burn-in and electrical testing. Burn-in testing accelerates failure mechanisms by electrically exercising the devices, or units under test (UUT), at elevated temperatures, thus eliminating potential failures that would not otherwise be apparent immediately or at ambient test conditions. Electrical testing includes functional and parametric electrical performance tests of the semiconductor device.
It would also be desirable to permit testing of unpackaged, singulated die in a manner similar to that accomplished with packaged semiconductor devices. Burn-in and electrical testing of unpackaged die would result in reduced material waste, increased profits, and increased throughput. However, such testing requires a significant amount of handling of the unpackaged die. Therefore, with unpackaged die, carriers must be provided to temporarily package the die for testing and certification of known good device (KGD). The test carrier must be compatible with electrical test and burn-in procedures while securing the die without damaging the die at the bondpads or elsewhere during the process.
FIG. 1 shows a conventional test carrier 11 for testing unpackaged semiconductor devices in accordance with the prior art. The test carrier 11 provides a base 13 configured to house a die 21, and to couple the die 21 and the testing device (not shown). The test carrier 11, includes the base 13 with a die receiving cavity 17; a cover 15 for retaining the die 21; and an interconnector 41 for establishing temporary electrical communication between the die 21 and the base 13; and a force applying member (not shown) for biasing the die 21 against the interconnector 41. The interconnector 41 includes contact members (not shown) configured to electrically connect to the die bondpads 27, such as flat or bumped pads. A plurality of external connector leads 33 extends from the base 13. Electrical communication between the enumerated components 11, 13, 21, 33, 41 and the testing device (not shown) is made via a variety of techniques including bondpads and wire bonding (both not shown) and is discussed in detail below.
The test carrier 11 couples the die 21 to a testing device (not shown) having circuitry configured to apply test signals to the die 21. The test device can include a chamber for subjecting the die 21 to temperature cycling during testing, either heated for burn-in testing or cooling for testing below ambient. Test carriers of the type shown in FIG. 1, are shown and described, for example, in U.S. Pat. Nos. 5,302,891, 5,408,190, 5,495,179, 5,519,332, 5,929,647, and 4,899,107, which are incorporated herein by reference.
The test carrier could also permit testing of packaged or semipackaged semiconductor devices.
Still referring to FIG. 1, the interconnector 41 is placed in the base 13 and is electrically connected to conductors (not shown) on the base 13. The semiconductor die is then placed face down in the test carrier 11 and on top of a interconnector 41. Electrical contact is established between die bondpads (not shown) and contacts on the interconnector (not shown) by a biasing force. The interconnector 41 establishes electrical contact between the die 21 and the base 13, and is in electrical communication with conductors (not shown) on the base 13.
Referring now to FIG. 2, the interconnector 41 is used to electrically connect the die 21 to the base 13. The interconnector 41, generally formed of silicon, includes a plurality of raised contacts 43 that establish electrical contact with die bondpads 27 on the die 21. The interconnector 41 also includes a plurality of conductive traces 45 thereon that communicate with respective interconnector bondpads 47 on an upper surface of the interconnector 41. The interconnector bondpads 47 are connected to contact pads 37 by any convenient means such as wire bonding 46.
As shown in FIG. 3, the interconnector 41 establishes temporary electrical communication between the die 21 and the base 13. The plurality of raised contacts 43 on the interconnector establishes electrical contact with the die bondpads 27. The plurality of conductive traces 45 on the interconnector 41 electrically communicates with the respective interconnector bondpads 47. The interconnector bondpads 47 are connected to the contact pads 37 by any convenient means such as wire bonds 46. The contact pads 37 are in electrical communication with the external connector leads 33 via internal connectors 50.
One of the problems encountered with testing of the die 21 in the test carrier 11 is the physical stress caused by the biasing force applied to force the die bondpads 27 against the plurality of raised contacts 43 of the interconnector 41 to ensure a good electrical connection. Establishing a good electrical connection is further complicated by the fact that in many die configurations, the die bondpads 27 are recessed below the surface level of a passivation layer. Moreover, in conventional test carriers, such as test carrier 11, the cover 15 and the inner surface of the base 13, which are biased against opposite surfaces of the die 21, are rigid. However, the surface of the cover 15 and base 21 may not be entirely planar. As a result, localized forces may be exerted against the die 21, causing some of the die bondpads 27 to be in electrical contact with the interconnector 41 and others not. This problem may be exacerbated by differences in thermal expansion between the die 21 and the cover 15 and/or the base 13 during burn-in.
There is, therefore, a need for a test carrier that is capable of testing singulated, unpackaged die without causing it damage, particularly during burn-in testing.
A test carrier having an elastomeric interposer inserted between an interconnector and a test carrier base for testing unpackaged semiconductor devices is proposed. Such a test carrier precludes having to solder or fix with conductive adhesive the interconnector to the test carrier base, and lessens the amount of biasing force required for KGD testing. Advantages to using a elastomeric interposer include having shorter signal lengths, and the elastomer material of the elastomeric interposer provides a compliant force distribution mechanism for seating the semiconductor in the test bed carrier. The elastomeric interposer material also allows for thinner test carriers.
In a preferred embodiment, an elastomeric interposer is placed between a test carrier and an interconnector to provide an electrical connection between the interconnector and contact pads on the test carrier base. The elastomeric interposer is capable of conforming to the shape of the interconnector and the test carrier base contact pads to sufficiently establish electrical contact. Since the elastomeric interposer also provides a biasing force, less pressure is needed to establish electrical contact, and thereby reduces the risk of damaging a semiconductor die.
In another aspect of the invention, a second elastomeric interposer may be placed between the semiconductor die and the interconnector, in addition to a first elastomeric interposer between the interconnector and the test carrier. In this configuration, the biasing force used to secure the die is transferred through both elastomeric interposers so that potential damage to the die bondpads is further limited.